1. Field of the Invention
This invention relates to a semiconductor substrate and also to a method of preparing such a semiconductor substrate. More particularly, the present invention relates to a semiconductor substrate having a specific structure of a bonding interface and adapted to an electronic device or an integrated circuit prepared by using a single crystal semiconductor layer arranged on an insulator, as well as a method of preparing such a semiconductor substrate.
2. Related Background Art
MOS transistor integrated circuits take a major part in today's computers and have attained to a remarkably enhanced level of operating performance or operating speed and that of integration for binary digital logic ULSI systems by means of processing techniques adapted to extremely reducing processing dimensions on the basis of the so-called scaling rule. However, as a gate length of less than 1 .mu.m is realized for MOS transistors, representing the available minimum processing dimension, as a result of the dimensional reduction brought about by the development of processing techniques, miniaturized MOS transistors come to be affected by various parasitic effects including the short channel effect that partly annul the improvements in the performance of the transistors due to miniaturization.
A silicon on insulator (SOI) device refers to a device formed in a single crystal silicon semiconductor layer arranged on an insulator and SOI devices have been attracting attention in recent years as they appear very promising for solving the problems attributable to the miniaturization of devices. More recently, SOI is also used to stand for semiconductor-on-insulator. In the initial stages of developing SOIs, efforts were paid to exploit the advantages of SOIs including a reduced parasitic capacity, a high radiation-proof effect and a latch up free effect that cannot be provided by ordinary bulk silicon substrates to be used for ordinary silicon ICs. More often than not, relatively thick silicon layers were used. More recently, however, it has been found that a fully depleted SOI device obtained by depleting its entire silicon thin film layer having a thickness of less than 100 nm can effectively suppress the short channel effect. Fully depleted thin film SOI devices have advantages over conventional bulk devices that can be summarized in four items as listed below.
(1) Easy dielectric separation and full separability of devices make it possible to realize a simplified process and highly integrated devices. PA0 (2) A high radiation-proof effect leads to a high reliability of devices. PA0 (3) A reduced stray capacity allows devices to operate at high speed and low power consumption rate. PA0 (4) A reduced short channel effect and a design rule adapted to miniaturization can be realized because of the feasibility of producing full-depletion layer field effect transistors using a very thin silicon layer. PA0 (1) those of oxidizing the surface of a silicon single crystal substrate, partly exposing the silicon substrate by opening an window through the oxide film and then forming a silicon single crystal layer on the SiO.sub.2 through lateral epitaxial growth by using that part as seed; PA0 (2) those of using the single crystal silicon substrate as active layer and forming a buried SiO.sub.2 layer thereunder by means of an appropriately selected technique; and PA0 (3) those of bonding a silicon substrate with an insulating substrate and polishing or etching the silicon substrate to produce a single crystal layer having a desired thickness.
Generally, an SOI-MOS device is produced by using an SOI wafer as starting material and forming MOS transistors in it. Therefore, the quality of the SOI substrate that is used from the very start of the process of manufacturing an SOI device plays a role that is more important than anything in the subsequent steps of the manufacturing process to make the manufactured SOI device highly reliable and performing. In the past decades, a number of researches have been made to establish methods of preparing an SOI substrate, which may be classified into the following three groups:
However, methods of any of these groups are accompanied by certain drawbacks. Those of group (1) are not satisfactory in terms of controllability, productivity, uniformity and crystal quality and those of group (2) are also accompanied by the problems of productivity and of crystal quality, whereas those of group (3) are far from perfection from the viewpoint of controllability and uniformity.
Meanwhile, ELTRAN (epitaxial layer transfer by bond & etch back porous Si) SOI substrates have been proposed as high quality SOI substrates comprising an SOI layer that is extending over the entire surface of a substrate with an even thickness and showing an excellent degree of crystallinity along with methods of manufacturing such substrates (see, inter alia, Japanese Patent Application Laid-Open No. 5-102445 "Method of Preparing Semiconductor Substrate", Japanese Patent Application Laid-Open No. 5-217992 "Semiconductor Substrate and Method of Preparing the Same", Japanese Patent Application Laid-Open No. 5-217821 "Method of Preparing Semiconductor Substrate", Japanese Patent Application Laid-Open No. 5-217820 "Semiconductor Substrate and Method of Preparing the Same", Japanese Patent Application Laid-Open No. 5-275663 "Semiconductor Device Substrate and Method of Preparing the Same", Japanese Patent Application Laid-Open No. 5-275329 "Semiconductor Device Substrate and Method of Preparing the Same", Japanese Patent Application Laid-Open No. 6-342784 "Etching Solution for Etching Porous Silicon, Etching Method Using the Same and Method of Preparing Semiconductor Substrate Using the Same", Japanese Patent Application Laid-Open No. 7-249749 "Method of Preparing SOI Substrate" and Japanese Patent Application Laid-Open No. 7-235651 "Semiconductor Substrate and Method of Preparing the Same".) The proposed methods of manufacturing SOI wafers are characterized in that, with any of such methods, it is possible to produce a scarcely defective SOI layer because the pores on the surface of a porous silicon base are closed and sealed as a result of the heat treatment using H.sub.2 and conducted prior to the epitaxial growth step and that it is possible to produce an SOI layer that is relatively free from uneven thickness because the etch selectivity of porous silicon relative to an epitaxial layer is as high as 10.sup.5. Thus, the SOI layer that plays a major role of a semiconductor device is made very smooth and adapted to mass production so that consequently, high quality SOI substrates can be manufactured at low cost.
As for the methods of preparing an SOI substrate by bonding, techniques have been proposed for bonding a layer of a high melting point metal or a high melting point silicide and a layer of another high melting point metal or silicon by utilizing a silicidation reaction on the bonding interface (see, inter alia, Japanese Patent Application Laid-Open No. 6-151789 "Method of Forming Semiconductor Substrate", Japanese Patent Application Laid-Open No. 4-186815 "Method of Manufacturing Silicon-on-Insulator Substrate", Japanese Patent Application Laid-Open No. 4-148525 "SOI Substrate and Method of Manufacturing the Same" and Japanese Patent Application Laid-Open No. 59-224156 "Method of Manufacturing Insulator Separation Substrate"). With any of these methods of manufacturing an SOI wafer, the stress generated by the difference between the thermal expansion of Si and that of SiO.sub.2 that has been the problem of the bonding step is reduced to obtain a uniform bonding strength over the entire surface of the substrate by combining a high melting point metal or a high melting point silicide and another high melting point metal or silicon and utilizing a silicidation reaction on the bonding interface.
Additionally, a metal SOI substrate has been proposed as an outcome of the technological development for SOI substrates, where the above last two techniques are combined to produce a large diameter substrate and a device formed on it and adapted to operate at ultra-high speed (Japanese Patent Application Laid-Open No. 8-305356 "Semiconductor Substrate and Method of Preparing the Same"). Thus, it is now possible to realize a cold bonding process by exploiting the high crystal quality, the high controllability, the high productivity and the high uniformity of an SOI substrate achieved by the SOI substrate technology in combination with the above described metal reaction technology. Such an SOI substrate has an excellent insulating structure for producing a barrier layer against electromagnetic waves and realizing an improved heat releasing property and hence it can be used to produce an ultra-high density LSI that operates at ultra-high speed with an operating frequency of 10 GHz. Still additionally, the proposed method of manufacturing an SOI substrate is based on remarkable scientific achievements and adapted to eliminate external turbulences to make it highly functional and productive.
In short, a metal SOI substrate is excellent in that it is based on a novel concept of making the substrate function as a device. Metal SOI substrates are described, inter alia, in Japanese Patent Application Laid-Open No. 6-244416 and U.S. Pat. No. 5,650,650.
However, as a result of a series of experiments preparing specimens of SOI substrate as described above and then various devices in the specimens of SOI substrate for evaluation, the inventor of the present invention came to find that they are none the less accompanied by the following problems. With the structure of the proposed substrate, the metal layer to be used for the bonding/reaction and the metal layer to be used as barrier for protecting the device against electromagnetic waves are made of a same metal. Thus, if the former layer is to be bonded firmly, the bonding process needs to be conducted at high temperature for a prolonged period of time to make the profile of the bonding interface rather flat for the reaction and it is difficult to realize a steep profile. Therefore, it is necessary to produce a layer made of a uniform and stable reaction material for the bonding/reaction in order to realize a strong bonding effect and eliminate fluctuations on the reacted interface for the subsequent processing steps. However, with the structure of the proposed substrate, unintended reactions can take place on the bonding interface and the change in the volume of the layer due to the reaction gives rise to a change in the stress, which by turn entails the following problems. Firstly, stress is accumulated in the device layer on the insulating film. Secondly, the wafer can become warped by the stress. Thirdly, the layer characterized by the skin depth for barring the passage of electromagnetic waves is reduced. All these phenomena act to degrade the characteristics and the high speed operation of the device comprising the substrate.